A semiconductor module includes semiconductors, etc., each consisting of many circuit elements such as transistors, resistors, capacitors, etc. that are mounted on a wiring substrate and wired to each another so as to achieve required operations and functions. Various methods are employed for such wiring between each semiconductor chip and the wiring substrate. For example, one of the methods is wire bonding that uses gold wires and another is a flip chip method that bonds each semiconductor chip directly to the surface of an object wiring substrate. At the back side of the wiring substrate having the semiconductor chip, etc. are formed external terminals with solder balls.
A high density packaging technology includes two techniques: one is SoC (System on Chip) and the other is SiP (System in Package). The SoC enables a plurality of functions to be integrated into one system on a silicon chip and the SiP enables the functions of a memory, a CPU (Central Processing Unit), etc. to be integrated into one package. At present, attention is paid to the SiP technique as a supplemental technique for the SoC. Hereunder, there will be described how the flip chip method is applied to the SiP technique. FIGS. 3 and 4 show an example of a package structure obtained by applying the flip chip method to the SiP technique. In FIGS. 3 and 4, connection terminals (solder bumps 313) of a semiconductor chip 301 are disposed in accordance with the concept of area (full grid) arrangement. Actually, however, one or two rows of them at the outer periphery may be disposed in accordance with the concept of peripheral arrangement.
FIG. 3 is a schematic diagram of a semiconductor module having a semiconductor chip 301 mounted on a wiring substrate 303, as well as another semiconductor chip 302 stacked on the chip 301 by a chip stacking technique. The chip 302 is connected to the wiring substrate 303 of a base package with a wire 305. The semiconductor chips 301 and 302 are covered by mold resin 309. Under the wiring substrate 303 are provided solder balls 315. In FIG. 4, the semiconductor module has the semiconductor chip 301 mounted on the wiring substrate 303, then another semiconductor package 309 is stacked on the wiring substrate 303 by a PoP technique to be described later. In any of the cases shown in FIGS. 3 and 4, the wire bonding method can be employed. However, in order to correspond to signal processings that are speeded up more and more, the flip chip method should preferably be employed to connect the signal terminals to the wiring substrate 303.
The PoP (Package on Package) technique is one of the SiP techniques and used to stack packages one upon another. When compared with the chip stacking technique, at present the PoP technique has such merits as yield improvement, as well as productivity improvement and cost reduction achieved by easiness of test performance. The PoP technique also has other merits such as easiness of problem analysis in troubles occurrence and fast and high density packaging realized by a co-packaging method employed for passive parts. Furthermore, the PoP technique also enables packages sold on the markets to be mounted together, so its application is diversified. And the PoP technique can also correspond to various module forms and shapes flexibly, thereby improving the flexibility in module designing.
The flip chip method enables fast processings and effective utilization of wire bonding are as favorably. On the other hand, the flip chip method requires high temperatures for packaging processes and the temperature, when it is cooled to the room temperature, comes to change significantly in a wide range. Consequently, the thermal expansibility difference between the semiconductor chip and the wiring substrate becomes remarkable; thereby the semiconductor chip and the substrate are apt to warp significantly. In case of the wire bonding method, the temperature required for processes is about 150° C. In case of the flip chip method, the required temperature becomes 200° C. or over in some cases. Particularly, now that the number of terminals often exceeds 500 pins in most advanced semiconductor chips, solder is required to connect those pins with use of the flip chip method. And if the Pb solder is used, the required heating temperature becomes 220° C.
Furthermore, in case of the flip chip method, processes are varied among the semiconductor chips and among the materials used for the junctions of the wiring substrates. The processes employed in the flip chip method are roughly divided into two. One is the local reflow process, which uses such techniques as pressure bonding or the like to bond the surface of each semiconductor chip is faced to an object wiring substrate and bonded thereon. The other is the batch reflow process, which puts a plurality of such objects as semiconductor chips on multiple forming wiring substrates or a plurality of wiring substrates and they are flown together into a reflowing oven as are, thereby they are heated and bonded together respectively.
The local reflow process is described in various documents. JP-A-2004-47670 (Patent document 1) describes a method for pressing a heated semiconductor chip onto a substrate chucked and retained on a stage. The patent document 1 also describes a means for forcibly cooling the substrate from the side of the stage. JP-A-2000-260827 (Patent document 2) describes how to keep a temperature of an object circuit substrate lower than a temperature of an object semiconductor chip with use of a cooling device provided on a stage used to retain circuit substrates. As described in the patent documents 1 and 2, the methods reduce the difference of thermal expansibility between the substrate and the semiconductor chip, thereby preventing the package from warping. JP-A-HEI9-219417 (Patent document 3) describes a method for suppressing such package warping by heating and cooling so that the thermal profile becomes approximately the same between the substrate and the semiconductor device to be mounted on the substrate. Furthermore, JP-A-2000-294602 (Patent document 4) describes a method for directly heating an object chip entirely with use of a laser beam, thereby preventing the object package from warping and unstable connection.
In case of the local reflow process, wiring substrates can be fixed on a stage for heating and bonding, so the process can assure favorable connection for packages. Thus bonding failures cannot occur so easily between wiring substrates and semiconductor chips, which otherwise might occur due to warped wiring substrates in heating processes. In spite of this, bonding is required for each semiconductor chip, so the process is disadvantage in productivity. And in any of the methods described in the above four patent documents, the local reflow process is employed, so the productivity is low.
On the other hand, in case of the batch reflow process, a plurality of wiring substrates are disposed on a stage and a plurality of semiconductor chips are put on those substrates respectively, then they are flown together into a reflow oven, so the process is favorable in productivity. In this case, wiring substrates put on a belt conveyer are just transferred continuously; the substrates are not fixed on the belt conveyer. Consequently, bonding failures occurrence is still anticipated between semiconductor chips and wiring substrates due to the packages warped in a heating process. JP-A-2004-119594 (Patent document 5) describes a method for two or more ICs mounted on a substrate are put between one flat pressing part and one wiring substrate supporting part, then those two ICs are bonded onto the substrate together through an elastic part. Furthermore, JP-A-2005-203664 (Patent document 6) describes a method that uses a jig capable of correcting warping of wiring substrates. Even through, each of those methods described above still requires methods for preventing warping to be caused by a heating process without lowering the productivity to eliminate such bonding failures that might otherwise occur between semiconductor chips and wiring substrates. Particularly, now that wiring substrates are being thinned more and more, warping in heating processes comes to increase. And thinner semiconductor modules are kept required for mobile phones, etc., so bonding failures are becoming more serious problems.